1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to a method for semiconductor fabrication supervision and optimization.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the quality, reliability and throughput of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for higher quality computers and electronic devices that operate more reliably. These demands have resulted in a continual improvement in the manufacture of semiconductor devices, e.g., transistors, as well as in the manufacture of integrated circuit devices incorporating such transistors. Additionally, reducing defects in the manufacture of the components of a typical transistor also lowers the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
The technologies underlying semiconductor processing tools have attracted increased attention over the last several years, resulting in substantial refinements. However, despite the advances made in this area, many of the processing tools that are currently commercially available suffer certain deficiencies. In particular, such tools often lack advanced process data monitoring capabilities, such as the ability to provide historical parametric data in a user-friendly format, as well as event logging, real-time graphical display of both current processing parameters and the processing parameters of the entire run, and remote, i.e., local site and worldwide, monitoring. These deficiencies can engender nonoptimal control of critical processing parameters, such as throughput accuracy, stability and repeatability, processing temperatures, mechanical tool parameters, and the like. This variability manifests itself as within-run disparities, run-to-run disparities and tool-to-tool disparities that can propagate into deviations in product quality and performance, whereas an improved monitoring and diagnostics system for such tools would provide a means of monitoring this variability, as well as providing means for optimizing control of critical parameters.
Run-to-run control as practiced in high-volume, multi-product semiconductor manufacturing does not easily fit into the framework of traditional approaches to process control. A typical approach defines a process model with a given set of states, inputs, and outputs. In some cases, the model is static, and in others, the model changes over time. At each time step, inputs and disturbances affect the states, and outputs are measured. Then, the controller makes an update and the process repeats. One reason this approach is not always applicable is that there are often multiple processing tools as well as multiple products. In addition, of all the measurements important to a process, only a subset are generally made on each run. Determining how to do controller updates in this environment can be a challenging task.
A run-to-run controller relies on having a process model that is consistently correct from run to run. When the various processes run on the tool are significantly different, the controller may behave unexpectedly because a change to a new process can appear to be a large disturbance. In addition, it may take several successive runs of a given process for the controller to stabilize, but manufacturing constraints may prevent this from happening. It is desirable that the controller would determine optimal settings for all processes that must run on the tool, regardless of the order in which they appear.
An example of a system that exhibits this behavior is the chemical mechanical planarization (CMP) of inter-layer dielectric (ILD) layers. Due to differences in pattern density and processing history, each layer/product combination processes at a different rate. In addition, as each product is qualified to run on several toolsets, there are also systematic variations caused by differences between the tools. Thus, one of the many control problems is to determine the optimal settings for each product/layer/tool combination that arises. Additionally, the measurements that provide the controller with information (such as measurements of removal from product wafers and/or test wafer qualification events) are provided at asynchronous intervals based on operational rules without regard to the control problems.
Other parameters it would be useful to monitor and control are process parameters related to rapid thermal processing (RTP). Examples of such process parameters include the temperatures and lamp power levels that silicon wafers and/or workpieces are exposed to during the rapid thermal processing (RTP) used to activate dopant implants, for example. The rapid thermal processing (RTP) performance typically degrades with consecutive process runs, in part due to drift in the respective settings of the rapid thermal processing (RTP) tool and/or the rapid thermal processing (RTP) sensors. This may cause differences in wafer processing between successive runs or batches or lots of wafers, leading to decreased satisfactory wafer throughput, decreased reliability, decreased precision and decreased accuracy in the semiconductor manufacturing process.
However, traditional statistical process control (SPC) techniques are often inadequate to control precisely process parameters related to rapid thermal processing (RTP) in semiconductor and microelectronic device manufacturing so as to optimize device performance and yield. Typically, statistical process control (SPC) techniques set a target value, and a spread about the target value, for the process parameters related to rapid thermal processing (RTP). The statistical process control (SPC) techniques then attempt to minimize the deviation from the target value without automatically adjusting and adapting the respective target values to optimize the semiconductor device performance, and/or to optimize the semiconductor device yield and throughput. Furthermore, blindly minimizing non-adaptive processing spreads about target values may not increase processing yield and throughput.
Traditional control techniques are frequently ineffective in reducing off-target processing and in improving sort yields. For example, wafer electrical test (WET) measurements are typically not performed on processed wafers until quite a long time after the wafers have been processed, sometimes not until weeks later. When one or more of the processing steps are producing resulting wafers that the wafer electrical test (WET) measurements indicate are unacceptable, causing the resulting wafers to be scrapped, this misprocessing goes undetected and uncorrected for quite a while, often for weeks, leading to many scrapped wafers, much wasted material and decreased overall throughput.
Metrology operations require a significant amount of capital and consume large amounts of cycle time in semiconductor manufacturing. Optimizing metrology may therefore significantly improve “fab” capital requirements and operating costs. However, traditional methods of optimization are often either based on ad hoc decisions and/or in some cases, careful statistical analysis to determine a “best” sampling rate for a given process/operation, balancing the improvements in control associated with increased sampling against the increased costs of such sampling.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.